The invention relates to data processing systems, and more specifically to the output circuits for data processing systems.
A large number of data processing systems operative with low power consumption have become available in recent years due to the development of CMOS technology. The demand for low power Consumption systems has also led to including standby modes in data processing systems, wherein clock pulses normally applied to the functional circuitry of the data processing system are blocked or discontinued during periods when the data processor is not performing a functional operation, and the output terminal of the output circuit is clamped at the high binary level.
If the peripheral circuit to which the output terminal is connected is a CMOS circuit, i.e., one with a high input impedance, the clamped output level does not present problems. However, if the peripheral circuit is a low impedance input circuit, such as a TTL circuit, current flows into the peripheral circuit during standby causing undesired loss of power during standby mode.
Alternatively, setting the output terminal at a high impedance during standby will suffice if low impedance TTL circuits are connected as the peripheral circuits, but such a set high impedance will adversely affect any CMOS peripheral circuit.
In other words, it has been necessary to select the type of the utilizing circuit to be connected to the processing system in accordance with the type of the output circuit of the system, and this results in complexity in designing the system and poor flexibility, and high performance cannot be obtained.